NEC adds L2 cache, DRAM controller to Vr processor

By
EE Times
(05/04/02, 10:55:35 PM EDT)

SANTA CLARA, Calif. - NEC Corp. has taken the wraps off a MIPS-based 64-bit embedded processor that integrates Level 2 cache and a DRAM controller, both equipped with error-correction coding features.

NEC, which announced the product at the Embedded Processor Forum in San Jose, Calif., said the new features in the Vr7701 are primarily aimed to please designers of storage-area networks and network servers, who tend to frown on memory access latencies and system malfunctions due to soft or transient errors. As a further enticement, the company has tied the processor to the PCI-X system bus and has added dual Ethernet media-access controllers.

As a rule of thumb, a processor doesn't get much of a performance boost if the internal clock frequency runs any more than four times faster than the system bus. With the system bus at 100 to 133 MHz and the processor clock frequency at 400 MHz, the 0.13-micron Vr7701 has reached that performance wall. Later versions based on 0.95-micron design rules reportedly will push the clock speed to 550 MHz.

"The extra clock speed doesn't help much, because once the pipeline stalls, it takes more cycles to go off chip and get the data from the DRAM," said Arnold Estep, senior marketing manager for Vr microprocessors at NEC.

But by bringing in a 256-kbyte (four-way set-associative) Level 2 cache, the processor will spend less time going off chip to fetch data, thus reducing memory latency. To further speed access times, the cache itself sports dedicated buses to the processor core, DRAM controller and on-chip bus, along with cache lock-attribute control.

In the event of an L2 cache miss, the processor can lean on its on-chip 64-bit memory controller rather than go off chip. The controller uses 128-byte burst transfers and shares a dedicated access path with the L2 cache.

The controller has hooks to fast double-data-rate synchronous DRAM running at a base clock speed of 100 to 133 MHz. For more cost-sensitive applications, conventional single-data-rate DRAM can also be used.

The L2 access port provides 1 Gbyte/second of sustained bandwidth over a 64-bit wide, 200-MHz on-chip bus for on-chip peripherals and I/O. The processor core and memory controller have 128-bit access points to the L2.

To hasten transactions to and from the PCI-X bus, the L2 cache tag is referenced to each I/O request. Access is sped further through a dedicated direct-memory-access port to the L2 cache.

In its next spin of the Vr7700 series, NEC said it may incorporate HyperTransport I/O. The company also is evaluating 3GIO and Infiniband.

NEC also added 64-bit plus 8-bit single and double error-correction code to the memory controller and L2. ECC is a must for network servers, switches, routers and network storage applications, the company said. "It's always been a requirement for storage and RAID devices. And now that storage and networks are moving closer together, they want ECC in the DRAM," Estep said.

The Vr7701 will sample in June. Housed in a 500-pin ball grid array, the processor will sell for $70 in 10,000-unit quantities starting in the fourth quarter.

More Embedded Processor Forum coverage.