Virage Targets Low Power SRAMs, ROMs at portables

By EETimes Services
iApplianceWeb
(07/30/02, 01:13:45 AM EDT)

Fremont, Ca. -- Seeing gold in the miserly power budgets ofmobile iappliance devices, memory designer Virage Logic Corp. is releasing a pair of single-port SRAMs that consume two to three times less power than current devices and a ROM that improves power savings twenty- to forty-fold, the company said.

Virage hopes to woo designers of high-performance portable devices, such as PDAs, laptops and 2.5/3G cell phones, that not only burn power when used, but also when just lying around. "Active power still dominates, but the leakage current is increasing rapidly in 0.13 micron and below. In 90 nanometers it's really high, compared to 0.13," said Krishna Balachandran, director of product marketing at Virage.

Increasing leakage current has raised the importance of lowering standby power, though it's still considerably smaller than active power consumption. However, many mobile devices, especially cell phones, spend most of their time in standby mode. So when conceptualizing its new memories, Virage applied a simple principle: if it's not being used, turn it off.

The SRAMs use several tricks to reduce power. First, the memory array is sliced up into banks that employ a sleep mode. When the memory is in use, banks with the relevant information turn on while the others remain off, reducing active power consumption. Within each bank, there are further layout changes, too. For instance, a divided word line scheme means only half the bit lines are active at any time. And a higher number of banks trims bit line length, thereby reducing capacitance, one of the major factors in power consumption.

The SRAM array also includes two clocks, one for reading and another for writing. Because reads take less time than writes, one of the clocks may shut down before the other. In traditional implementations, one clock controls both functions and must compensate for the worst-case scenario in each one. Virage's way will cost designers some extra space, but it saves power.

More means less

A final change to the array also includes a greater number of latched sense amplifiers, one for each bank. In this case, more means less. Sense amplifiers are used to detect and amplify changes in the voltage of signals within the memory. They use a lot of power to do so. Typically, without banking, memory arrays require large sense amplifiers that consume more power. With banking, there can be a higher number of smaller amplifiers that consume less power because they are turned off in unused banks.

Virage's new crop of designs builds on its recently released line of high-speed Self Test and Repair (Star) memories and a slightly older product line dubbed Area, Speed and Power (ASAP). Virage says its 0.13-micron ASAP ultralow-power SRAM is 1.81 mm2 in a 512-kbit density, about 16 percent bigger than regular offerings from competitors. For the ASAP and Star ultralow-power SRAMs, the combination of banking, plus divided word lines enable the memories to operate at 0.046 mW/MHz worst case for a 256-kbit memory, the company said. Densities range from 128 kbits to 512 kbits. The SRAM is configured by users into one, two, four or eight banks. On the ROM, the banking is automatically configured depending on size.

For the Star ultralow-power ROM, Virage is touting the reduction in standby leakage as a "breakthrough." The company claims a 20x to 40x savings, depending on the configuration and the competing device. In a 1-Mbit memory, power consumption is 0.031 mW/MHz in the worst case. The ROMs can be generated ranging in density from 64 kbits to 16 Mbits.

Architectural change

The reduced power consumption comes from an aggressive change in the architecture, which also helped reduce its size by 23 percent. A traditional ROM uses two word lines and a bit line. A transistor connected to the bit line generates a zero, because there is a path between the bit line and the ground on the other side of the transistor. If there is no connection, the transistor generates a one because there is no path and no discharge.

When a zero is generated, there will be leakage current because of the connection, even in standby mode. But in the Virage design, there is no connection to the ground, which is eliminated. Instead, a source line has been added. "There is no [voltage] difference between the source line and the bit line when the word line is not turned on. Therefore there is no discharge or leakage path and no current consumed. This is a very unique way of implementing a ROM," Balachandran said.

Also, in the programming of the ROM, the company has implemented a patented technique it calls "active control." When data is saved on the ROM, the programming method cuts down on the number of active bits (zeros) saved because they consume more power than passive bits (ones).

The SRAM embedded memories will be available first on Taiwan Semiconductor Manufacturing Co.'s 0.18-micron and 0.13-micron logic processes, while the ROM will be available first on TSMC's 0.13-micron process. Both designs have already been used by two chip makers at 0.18-micron design rules.

Design kits and other front-end tools are available now and production will be phased in between now and the fourth quarter. Pricing for the kit and tools for the ASAP ultralow-power SRAM starts at $57,000; for the Star ultralow-power SRAM they start at $130,000; and for the Star ROM they start at $200,000.