Tensilica multicore Xtensa V Reaches 350 MHz

By Bernard Cole
iApplianceWeb
(08/26/02, 03:58:54 AM EDT)

Santa Clara, Ca. --- Tensilica, Inc. has released the newest version of its Xtensa V core design which runs at 350 MHz and can support multiple, unique processors in system-on-chip (SOC) architecture.

The new version of its configurable and extensible processor architecture is supported by the same software development, hardware and EDA tools as the earlier CPUs in the family. Changes made by the designer to extend the Xtensa processor hardware - adding instructions, registers, processor state and custom execution units - are immediately and automatically reflected in the entire software tool chain.

In addition to support for multiple unique processors has added a number of new capabilities. For systems requiring shared memory / bus architectures, a new write-back cache option reduces system bus traffic has been used to boost system performance. Also added was a processor ID register to the instruction-set architecture (ISA) that can identify each unique processor integrated on a SOC to ease software development in natively parallel applications that deploy multiple copies of the same configuration of the Xtensa processor.

The core architecture also has an improved local memory interface (XLMI) to enable the attachment of multi-cycle devices with variable latency. An incoming Request feature enables simultaneous execution of instructions and handling read/writes to the processor's local data memory from external agents such as DMA engines or other tightly coupled processors.

With configurable interface widths up to 128 bits, the Xtensa processor has a peak I/O bandwidth of 45Gb/sec. Also enhanced are processor-to-processor and RTL-to-processor communication.

Improvements have also been made to the TIE language with the ability to generate the new instructions, registers, state variables and complex execution units using the Tensilica Instruction Extension (TIE) language. TIE can also support designer-defined conditional load and store instructions, which results in code that utilizes fewer branch instructions which often limit overall performance.

The company says it has tuned both the design and tool flow to consistently achieve worst-case performance of 350 MHz in a 0.13-micron process for typical Xtensa V configurations through improvements to the physical design flow, including automated scripting of Synopsys Physical Compiler-based design flow.

Tensilica has optimized the Xtensa C-compiler (XCC) with such new capabilities as cross-file inlining, interprocedural analysis and removal of unused functions, improved alias analysis and register scheduling, and numerous code generation improvements.

In each of the four EEMBC benchmark suites - independently certified benchmarks developed to measure the performance of processors in a variety of embedded applications - it was determined that head to head against the ARM1020, the base Xtensa processor is 43 to 256 percent faster on out-of-the-box EEMBC benchmarks, while the optimized Xtensa core outperforms the ARM1020 8X to 33X.

Another universal yardstick for measuring processor performance is the Dhrystone benchmark (v2.1). The Xtensa V 32-bit core delivered 2.0 DMIPS/MHz with full optimization, and 1.2 DMIPS/MHz with no in-lining. By comparison, the ARM 1020E deliveres 1.7 and 1.2 DMIPS/Mhz, respectively. The recently introduced MIPS M4K 32-bit core delivers 1.35 DMIPS/MHz with full optimization, while the MIPS 5KCc 64-bit core delivers 1.4 DMIPS/Mhz, also with full optimization.

Available now, licensing fees for a single processor configuration, including a complete, configured GNU-based software development toolchain, start at $350,000. The Xtensa C compiler, Xtensa instruction set simulator, and Xtensa TIE compiler are priced separately.

For more information, go to www.xtensa.com.