Toshiba proposes new magnetic RAM structure

By Bernard Cole
iApplianceWeb
(09/25/02, 10:00:07 PM EDT)

Tokyo, Japan --- Continuing the industry momentume toward a nonvolatile and fast access memory device more appropriate to to the power and reliability needs of small footprint iappliances, Toshiba Corp. has developed a magnetic random-access memory (MRAM) with a double-tunnel-junction structure.

The company said that this is an important step toward its goal of boosting boosting MRAM density to the 1Gb level, more than macthing the theoretical direct memory access of the 32 pit CPUs used in many such devices. MRAMs, in addition to allowing access to memory roughly equivilant to present DRAMs, would make it possible to do away with the use of nonvolatile flash memory devices, and significantly lower power requirements. Use of such devices would allow preservation of important information in memory, should batteries fail on such devices.

At the 26th annual meeting of the Magnetic Society of Japan, the company's reearch team said that one of the major challenges to realizing large-density MRAM is raising the signal output (sense voltage) from each cell. Earlier this month, the company announced a partnership with NEC Corp. to develop a 256Mb MRAM. Equally urgent, Toshiba engineers said, is establishing a finer process for magnetic-tunneling-junction (MTJ) cell fabrication.

By introducing a double-junction structure, Toshiba claimed it has solved both problems, and succeeded in doubling the signal output even when about 1V is applied.

Toshiba developed a test memory array by fabricating MTJ cells on CMOS switches in a 0.18µm process. By introducing a double-tunnel-junction structure in the MTJ cell, the team verified that the cell worked as a memory with a large signal output, about twice larger than thus far reported.

An MTJ, or tunneling-magnetoresistive (TMR) element, has a multilayer structure of a very thin insulating layer (the tunnel barrier) sandwiched by magnetic layers. When both magnetic layers magnetize in the same direction, tunnel current flows through the barrier and magnetoresistance decreases. This is the "0" status. When the two layers are magnetized in opposite directions, tunnel current does not flow, resulting a high resistance - the "1" status.

When the voltage applied across the junction is small, the resistance difference (the magnetoresistance ratio) between the two statuses is large enough, at nearly 50 percent. But when the applied voltage goes above 0.4V, the MR ratio decreases nearly by half and signal output from the cell becomes low. "At present, the signal output barely satisfies the requirement for a 64Mb memory, but it is far short for a larger-density part," said Yoda.

Toshiba engineers built the double-tunnel barrier structure using undisclosed materials. While conventional single-junction TMR elements consist of three layers, Toshiba's double-junction TMR element has five. The magnetic layer that switches magnetized direction is at the center, sandwiched by tunnel barriers. They in turn are surrounded by layers with a fixed magnetized direction.

A 200mV signal output, or ±100 mV, is considered the requirement for a 1Gb memory. Toshiba's test chip achieved a signal output of more than ±90 mV. By optimizing materials for the central magnetic layer, Toshiba engineers expect that the signal output can be further increased. Though the structure is more complex, the researchers believe that the performance of the MTJ cell with double junctions is sufficient to justify the increased complexity.