Network Processing Forum Proposes NPU APIs

San Jose, Ca. -- The Network Processing Forum has unveiled four separate software application programming interfaces that together constitute a framework for developing open-interface systems using network processors.

By creating an infrastructure for service-specific APIs, the NPF hopes to make it easier for software and hardware developers to begin work on open interfaces. Known as "implementation agreements," the four suites are available for free public use.

Work on the four APIs began when the NPF was still known as the common processor interface (CPIX) coalition. Network processor and system vendors tried to come up with specific APIs with open interfaces that corresponded to device- or system-level services, only to find that their ways of defining terms and creating software interfaces did not always correspond across vendor implementations.

The suites are: a software API framework; a software API lexicon; software API conventions; and an interface management API.

First among equals amonsgst the new API specs is the one for the software API framework, because it provides the infrastructure on which all APIs are released. The lexicon and conventions agreements then create standard terms and ways of describing interfaces across architectures. The interface management API provides a common software means for configuring and managing both physical ports, such as SPI-4, as well as logical ports on the data-link layer.

With the framework completed, NPF now can work on APIs on three fronts: functional APIs on the device layer; functional APIs on the element abstraction layer; and reference functions common to a specific processor, such as classification, modification and traffic management.

NPF services APIs on the system abstraction layer include network-level services such as IP version 4, multiprotocol label switching, and differentiated services. NPF operational APIs include multilayer functions such as naming spaces and packet-handling conventions. All APIs will interface with specific processor chips using the message-passing protocols developed in the Internet Engineering Task Force's ForCES group.