Philips: configurable CPU matrix lowers cost, power, boosts speed

By Chris Edwards
iApplianceWeb
(10/24/02, 02:42:47 AM EDT)

Eindhoven, The Netherlands --- Research at Philips Semiconductors indicates that mactrices of configurable processors on a single die may be the best way to achieve high performance and low power, as well as provide a way to amortise the huge cost of chip design across multiple projects.

An approach recommended by leading academics such as Professor Hugo de Man of the Catholic University of Leuven, Philips has experimented with parallel custom processors and found that die-size efficiency and power can approach and possibly exceed that of custom logic.

Bob Payne, Philips' US chief technology officer, said: “When I started to design ICs, performance was the biggest concern. In management it was cost. Now it is power.”

The company has used the Adelante Saturn DSP platform to experiment with an on-chip multiprocessor. The Saturn platform uses customised processors called AXUs that run under the control of a host risc processor.

Payne said: “Designing for lower power could give higher speeds. With multiple AXUs, you can get higher performance at a given clock speed.

“A 1GHz mono-processor has to run at maximum voltage but a farm of 100MHz processors can probably run at minimum voltage, so you get a V-squared advantage.”

On die size, Payne contends that an instruction sequencer with high-density memory can be more die-space efficient than a synthesised finite state machine controller.

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