Moto Unveils 610 MIPS 32 bit ColdFire CPU core

By Bernard Cole
iApplianceWeb
(10/26/02, 10:54:53 PM EDT)

Austin, Texas -- Looking to strengthen its postion in a wide variety of embedded applications at the network infrastructure edge and in a variety of connected idevices, Motorola Inc. has debuted its next generation 610 MHz ColdFire superscalar CPU core.

At 333 MHz and 610 million instructions per second (MIPS) in 0.13 micron process technology, the V5 core offers significant performance increases over the V4 ColdFire core, previously the highest performing ColdFire core on the market.

The superscalar microarchitecture of the V5 core increases the number of instructions that can be executed simultaneously, thereby increasing the performance of the core. With dual execution pipelines and a larger branch cache, this next-generation core provides a 2x performance increase compared to a 220 MHz MCF5407 device, a V4-based standard product.

In the future, architectural enhancements such as improved branch prediction and dual multiply-accumulate units will increase this processor's performance efficiency from 50-200% depending on the application.

ColdFire processors are used in a wide range of applications from connected consumer entertainment such as set-top boxes to embedded networking systems such as routers as well as portable devices such as MP3 players.

Originally developed as a subset of the M68000 family instruction set, the new ColdFire core moves far beyond its historical legacy through the use of number of new architectural enhancements.

For example, the new implementation features a 4-stage, 64-bit instruction fetch pipeline that feeds two instantiations of the 5-stage operand execution pipeline and leverages micro-architectural technology from the MC68060 and the V4/V4e ColdFire designs.

It also incorporates a superscalar enhanced multiply-accumulate unit (EMAC) for digital signal processing functions and is engineered to support simultaneous dispatch and execution of 2 multiply-accumulate instructions per cycle to the EMAC and supports extensions to the EMAC instruction set. This allows “single-product/double-accumulation” operations for improved performance of key signal processing algorithms, such as those involved in Fast-Fourier Transforms (FFT) and Discrete Cosine Transformations (DCT).

On-chip hierarchical branch acceleration logic in the instruction fetch pipeline includes a 256-entry branch cache memory with both global and local prediction state information, a 128-entry global prediction table for accesses which “miss” in the branch cache, and a 4-entry last-in, first-out hardware return stack.

To allow developers to balance performance versus power consumption/dissipation, the new architecture is configurable by the designer over a range of local memory sizes (including cache) and optional execution units: double-precision floating-point unit (FPU) and virtual memory management unit (MMU), both compatible with the V4e core, are available as options.

Go to www.motorola.com/semiconductors for more information on this product.

For more information about the issues, products and technologies in this story, go to the  iAppliance Web Views  page and call up the associatively-linked XML/Java Web map of the iApplianceWeb site and search for product information since the beginning of 2002.

For technical article coverage, go to EETimes In Focus maps on the same Web page and browse or quickly search for all articles on a particular topic since the beginning of 1998.

These Web Maps can be browsed by date, by category, by title, or by keyword, with results displayed instantly either as a list of possible hits or with the specific Web page.