Stretch debuts software configurable net processor

By Bernard Cole
iApplianceWeb
(04/27/04, 3:22:09 PM PT)

 Mountain View, Ca. -- By integrating a programmable logic core into the very heart of an off-the-shelf processor and combining it with a unique software architecture and tool suite, Stretch Inc. believes that the combination will attract embedded and  iA system developers to its door. 

The suite is the leading edge of its just introduced S5000 family of software configurable processors. According to Gary Banta, Stretch CEO, the new hardware/software architecture is designed to enable developers to automatically configure and optimize the processor using only standard C/C++ code, not escoteric VHDL code, nor any of the C and C++ variants targeted at hardware generation. 

He said this was achieved in its new Stretch S5 engine by using Tensilica's  Xtensa RISC processor core in combination with the company's Stretch Instruction Set Extension Fabric (ISEF). 

Banta said the ISEF is a software-configurable data-path based on proprietary programmable logic. Using the ISEF, system designers extend the processor instruction set and define the new instructions using only their C/C++ code. 

"As a result, developers get the performance of logic with C/C++ development simplicity -- achieving unprecedented performance, easy and rapid development and significant cost savings," he said. 

Currently, he said,  embedded system developers are forced to make painful compromises when addressing compute-intensive applications. Their choices include using banks of DSPs or GPPs, resulting in costly and difficult-to-program multiprocessor systems; selecting fixed-function chips, which do not allow them to address changing standards or differentiate their products; or mixing processors and FPGAs or ASICs, which requires the design of custom hardware, greatly increasing time-to-market and development costs.

Banta said that conventional wisdom is that clock rate determines processor performance -- and that higher performance at the same clock rate requires complex fixed-instruction-set architectures (e.g., VLIW, SIMD) that are difficult to program and are effective only in certain applications. 

The company is able to turn this on its head through the use of  configurable instructions that reduce program "hot spots" (sequences of operations that must be repeated many times) into single instructions. 

"On conventional processors such as DSPs, optimization of hot spots is usually done by a programmer using low-level assembly code, which directly represents the sequence of processor operations one by one," said Banta. "Compilers automate this task, but only with a significant loss in performance. Further, because each operation is very simple, tens to hundreds of assembly instructions are needed to implement each hot spot."

On the S5000 processor, an entire hot spot -- expressed only in C/C++ -- is reduced to a single instruction. He said the  the software developer first identifies hot spots using a profiling tool. Then the C/C++ source code from the hot spot is automatically compiled into an ISEF configuration, creating a single custom instruction that implements the entire hot spot. 

Stretch's off-the-shelf S5000 software-configurable processor family debuts with three members, all based on the S5 engine. The products differ only in their I/O and packaging, said Banta, allowing the products to even more precisely match the needs of specific markets. 

An intuitive graphical Integrated Development Environment ($900 single-user license) includes the Stretch C Compiler, instruction-set simulator, profiler and debugger enabling developers to port, profile, accelerate, and optimize applications quickly. Run-time support includes a StretchBIOS toolkit of run-time code and MontaVista Linux for embedded real-time Linux systems.

For more about the Stretch architecture, the new devices and tools, and pricing, go to www.stretchinc.com. 

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